Taiwan Semiconductor (TSMC) released its second-quarter financial report for 2024 (ending in June 2024) before the US stock market on the afternoon of July 18, 2024 Beijing time.
Below is the summary of TSMC's 2024 second-quarter financial report conference call. For the interpretation of the financial report, please refer to " ASML and Trump's Continuous "Feints"? What's TSMC Afraid of! ".
I. $Taiwan Semiconductor(TSM.US) Financial Report Highlights:
II. Details of TSMC's Conference Call
2.1. Key Points from Executive Statements:
1) Business Highlights:
Short-term Demand Outlook:
- Third Quarter Outlook: The business is expected to be strongly supported by demand from smartphones and AI in the third quarter.
- Full-Year Outlook for 2024:
Industry: The overall semiconductor market (excluding memory) is expected to grow by approximately 10% in 2024 (consistent with the previous quarter's expectations).
Market Share: TSMC held a 28% market share in the foundry industry in 2023 and is expected to further increase in 2024.
Revenue Expectations: Revenue for 2024 is expected to grow slightly above mid-term growth at 20% in USD (slightly better than the previous quarter's expectations, relatively optimistic).
Expansion of Foundry Industry Definition:
- New Definition of "Foundry 2.0": Includes packaging, testing, mask manufacturing, and all IDMs (excluding memory manufacturing).
- 2024 Growth Forecast: The growth rate of the foundry industry under the new definition is expected to be close to 10% in 2024.
Technological Innovations:
- 2nm Technology: The number of new designs in 2nm technology in the first two years will exceed that of 3nm and 5nm in their respective first two years, with mass production expected in 2025.
- N2P Technology: Building on N2 to further improve performance by 5% or reduce power consumption by 5% to 10%. It will support smartphones and high-performance computing applications, with plans for mass production in the second half of 2026.
- N16 Technology: Featuring Super Power Rail (SPR) and introducing a new backside contact scheme for the first time. Compared to N2P, N16 provides an 8% to 10% speed improvement at the same power consumption or a 15% to 20% power improvement at the same speed, along with a 7% to 10% increase in chip density. Suitable for specific high-performance computing products, with plans for mass production in the second half of 2026.
Financial Highlights:
Revenue: Revenue in the second quarter increased by 13.6% (New Taiwan Dollar) or 10.3% (US Dollar) quarter-on-quarter, driven by strong demand for 3nm and 5nm technologies, partially offset by seasonal factors in the smartphone sector.
Gross Profit: Gross margin increased by 10 basis points to 53.2% quarter-on-quarter, mainly reflecting cost improvements and favorable exchange rates, partially offset by the impact of N3 RAM gross margin.
Key Financial Ratios:
- Accounts receivable turnover days decreased by 3 days to 28 days.
- Inventory days decreased by 7 days to 83 days, mainly due to increased shipments of N3 wafers.
Guidance:
- Revenue: Expected third-quarter revenue to be between USD 22.4 billion and USD 23.2 billion, a 9.5% increase quarter-on-quarter and a 32% increase year-on-year.
- Gross Profit: Expected third-quarter gross margin to be between 53.5% and 55.5%, operating profit margin between 42.5% and 44.5%.
- Capital Budget: The 2024 capital budget has been raised to between USD 30 billion and USD 32 billion (previously expected USD 28-32 billion), mainly for advanced process technology (70% to 80%), specialty technology (10% to 20%), and advanced packaging, testing, and mask manufacturing (10%).
2.2 Q&A Analyst Q&A
Q: What are the new views on the supply and demand balance of AI accelerators and advanced packaging capacity?
A: We are working hard to achieve supply-demand balance, but currently the demand is too high to balance. We are working to meet customer demand, and capacity continues to increase. We hope to achieve balance by 2025 or 2026.
Q: It was mentioned earlier that the compound annual growth rate of CoWoS capacity in the coming years is 60%. How much capacity expansion is planned for next year?
A: We are committed to increasing capacity in any possible scenario. The tight supply situation is expected to continue until 2026. For next year's capacity plan, we expect to continue significant capacity growth. Despite doubling capacity last year, we may further increase capacity next year to exceed last year's growth rate.
Q: Given the current situation, what should we expect for TSMC's future gross margin? Will it return to the 50% to 60% level in 2022?
A: Some key factors affecting gross margin beyond 2025 include: 1. With the introduction of N3 technology, we expect cost dilution to decrease. We are committed to increasing product value, reducing costs, and improving production efficiency, which is our strength. 2. We may transition from N5 technology to N3 to address strong market demand. While this transition may have a short-term negative impact on gross margin in the implementation year, it is expected to have positive effects in the long run. 3. We are facing cost challenges related to inflation, including rising electricity prices. 4. Next year, we will start production at two overseas wafer fabs in Arizona and Kumamoto. These overseas wafer fabs are expected to lower our gross margin by 2 to 3 percentage points next year and in the following years +Despite these challenges, we are confident in achieving a gross margin of over 53% through cost management efforts between overseas and Taiwan wafer fabs.
Q: With TSMC accelerating its overseas expansion, how will subsidies and ITC credits affect costs and gross margins? What impact do these subsidies and credits have on TSMC's overall capital expenditure and total spending?
A: Typically, subsidy income is reflected in the cash flow statement and used to offset the corresponding asset value on the balance sheet. Once the relevant wafer fabs start production, their impact on the income statement will be evident. Different countries' governments have different strategies for providing subsidies. By referring to our financial statements, you can see the actual subsidies received in the previous fiscal year and the previous quarter. For example, in 2023, we received over $1.5 billion in subsidies, mainly from Japan.
Q: Can you elaborate on TSMC's progress in enhancing product value sales? Do you anticipate any capacity shortages next year? Will this provide TSMC with more opportunities to sell value to customers?
A: Our pricing strategy is strategic. Currently, this strategy is progressing smoothly and will continue to be implemented continuously. We are committed to delivering our value, and customer performance is also outstanding. Therefore, we also look forward to achieving good performance.
Q: How is the pricing strategy formulated? At the same time, will high-performance computing (HPC) customers have different pricing from smartphone customers? Do you expect a very high demand for advanced nodes next year?
A: The pricing strategy is strategic and does not adopt a uniform standard for all product departments. Therefore, pricing for different customer groups will vary. Currently, there is a continuous increase in demand from customers for leading technology capacity, and we are working closely with them. We are committed to providing maximum support in pricing and capacity.
Q: What measures will TSMC take to address the increasing geopolitical risks, especially considering the U.S.'s dependence on TSMC chip production in Taiwan? Does TSMC plan to further expand its capacity in the U.S., and would it consider sharing ownership with the U.S. government? Regarding the shipment of chips to U.S. customers, does TSMC need to pay U.S. tariffs?
A: Currently, we have not adjusted the original plans for overseas wafer fab expansions, and we continue to expand in Arizona, Kumamoto, and possibly in Europe in the future. Our strategy remains unchanged. As for joint ventures, we have no such plans. As for tariffs, to our knowledge, if there are import tariffs, they are usually borne by the customers, and there are currently no further discussions or related matters.
Q: Given the continuous growth in technological value, why doesn't TSMC reassess and raise its long-term gross margin target of over 53%?
A: We are working hard with customers and enhancing our value through strategic pricing strategies. Currently, we reaffirm the target of over 53% and emphasize the "above" part. At this stage, I do not intend to adjust this target. In the future, with deeper communication and discussions with customers, we may reassess and provide a higher target
Q: With the growth and expansion of CoWoS demand, is the profitability of advanced packaging approaching or exceeding the company's average level? Considering the current supply chain constraints, is TSMC considering increasing partners to increase CoWoS capacity to support customer growth?
A: The gross margin of advanced packaging used to be significantly lower than the company's average level, but it is now gradually approaching. Through efforts in economies of scale and cost control, we have significantly improved the gross margin. This indicator has shown significant improvement in the past two years.
Regarding cooperation with OSAT partners, we are actively advancing. Due to insufficient CoWoS capacity and tight supply, this limits the growth potential of customers. To address this issue, we are working closely with OSAT partners to increase capacity to support customer growth and ensure the smooth sale of TSMC wafers.
Q: What are TSMC's capacity plans for the advanced nodes N2 and N16? Given that AI customers are actively migrating to the most advanced nodes, especially the interest in N16, can TSMC provide corresponding capacity support? Will N2 and N16 structurally become larger nodes compared to the past?
A: Customers are seeking more efficient energy-saving modes. Therefore, they are eager to adopt more advanced technologies to reduce power consumption. Many customers are quickly transitioning to N2, N2P, and N16 nodes. We are working tirelessly to expand capacity to meet these demands. Currently, capacity is very tight. We expect to establish sufficient capacity to support this demand in the next year or two. Although the demand is not fully met at the moment, we are working hard to achieve this goal.
Q: N3 uses fewer EUV layers and has lower capital intensity. So, as N3 production gradually increases, does N3E structurally enhance the overall return and gross margin of the entire N3?
A: We do not differentiate between different nodes within the family. Overall, N3E will take longer to reach the copper mark, typically around 8 to 10 quarters. As for N3, we expect it to take 10 to 12 quarters.
Q: Considering that TSMC may convert N5 tools to support N3 capacity, should investors consider N5 and N3 as one large node? Will TSMC continue to leverage tool commonality to provide flexibility and switch between different nodes?
A: 12 and 16 belong to a large foundry, 7 and 10 form a large family, however, 5 and 3 are not considered one family. Nevertheless, the tool commonality between 5 and 3 nodes exceeds 90%, and they are both located in the Tainan Science Park, making the conversion process very convenient.
Q: Are you considering doubling CoWoS capacity again by 2025? As customers migrate from CoWoS to more advanced versions, CoWoS ARM does not require TSV and large silicon interposers, does this help alleviate the CoWoS capacity constraints we face? Will this help achieve the goal of supply-demand balance by 2025 or 2026?
A: CoWoS-R, CoWoS-L, etc., these are all based on customer demand. Even for the same customer, different products have different technical paths. When we double our production capacity, we consider the different versions of CoWoS. Specific details on which version will double or grow more are related to customer demand and cannot be disclosed.
From last year to this year, our production capacity has already doubled. We plan to double again from this year to next year, and possibly even more. For this, I need to collaborate with OSAT partners to increase supply to support customers. Different versions of CoWoS do provide some flexibility, but each version has its specific toolset. Nevertheless, some tools can be used across all versions of CoWoS.
Q: In the next two years, will edge AI customers in the smartphone sector use SOIC or 3D IC? Will they continue to use info? Or will they consider other advanced packaging solutions?
A: When my customers migrate to 2 nanometers or N16, they may need to adopt the chiplet approach and use advanced packaging technologies. For edge AI and smartphone customers, compared to HPC customers who develop faster due to bandwidth and latency reasons, smartphone customers are more concerned with space occupation and added functionality. Therefore, my major customers initially adopted info packaging technology, and in the first two years, no other customers could catch up, but later they all caught up.
Q: In the next two to three years, what are the expected unit shipments and silicon content for smartphones and PCs? Have customers already started planning for 5-nanometer and 3-nanometer capacity by 2025 to address supply constraints? Do you have an estimate for the silicon content of smartphones AI in the next two to three years?
A: AI is very complex, and now all customers want to integrate AI functions into edge devices, so chip sizes will increase by about 5% to 10%. We have not yet seen a sudden increase in unit growth, but we expect AI functions to stimulate demand and shorten replacement cycles. In about two years, you will see a significant increase in unit growth for edge devices such as smartphones and PCs. We are working hard to expand our capacity to support our customers.
Q: With the current strong demand for generative AI, how is TSMC appropriately planning its capacity? How does TSMC manage the risk of demand fluctuations? In such an environment, how does TSMC avoid the risk of overbuilding capacity?
A: I have explained our capacity planning and investment discipline to ensure we do not repeat the mistakes of 2021 and 2022. This time, we carefully examine customer demand forecasts and study the actual applications of AI. Through internal testing, we found that AI can indeed significantly improve productivity. I am also in line to purchase products from customers, although I have no privilege, but I find them very useful. Therefore, I believe that this time the demand for AI is more real than two to three years ago. At that time, people were concerned about shortages, leading to supply shortages in various industries. This time, AI will be a key tool to improve productivity in daily life, whether it is in healthcare, industrial manufacturing, or autonomous driving Despite this, we still use both top-down and bottom-up approaches to discuss with customers and ask them to focus more on reality. I don't want to repeat the mistakes of two or three years ago, that's our strategy now.
Q: When introducing new technology that can save about 20% of electricity, can we assume that the total power consumption of the entire system can be reduced by another 20%? Based on your discussions with customers, can they also reduce total operating costs, leading to a situation where the more they buy, the more they sell?
A: You asked whether a 20% reduction in chip power consumption means a 20% reduction in total system power consumption. The answer may be negative because the entire system includes the power consumption of all components such as connections and processing. Unless each component saves 20% of power consumption, an overall 20% reduction cannot be achieved. However, accelerators or CPUs account for a significant portion of system power consumption, even if not 20%. That's why all customers want to use the most advanced technology and actively migrate to 2-nanometer technology.
Q: What is the biggest bottleneck in expanding production capacity?
A: Land, electricity, talent, etc.
Q: Recently at Computex, some companies announced their intention to accelerate product pace or product releases. How does this affect TSMC's capacity planning? What impact does it have on supporting customers?
A: We like this trend because TSMC is very good at leading technology development. Each product takes 1.5 to 2 years from design to completion, so we received this information very early. Customers announced this news because they are very satisfied, and we are also happy because they recognize our value.
We are ready. Not only because they announced it in June, but we have discussed with them and prepared for these changes well before.
Q: Is TSMC researching or exploring fan-out panel-level packaging technology? Will this become TSMC's medium- to long-term development direction?
A: We are researching panel-level fan-out technology, but it is not mature enough at the moment. I personally think it will take at least three years. Within these three years, we do not have a solid solution for cases where the wafer size is more than 10 times the radiation size. Currently, the largest chip size we support is 5 times the radiation size. I believe that in two years, panel-level fan-out technology will start to be introduced, and we are working hard to achieve this goal.
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