"Little Nvidia" challenges multiple giants, Astera will be listed tonight

Source: Semiconductor Industry Watch, compiled from semianalysis.

Astera (ALAB) will be listed on Wednesday night, attracting attention as a unicorn in the booming AI field.

The gold rush for artificial intelligence infrastructure is creating huge opportunities for companies providing supporting technologies. Not everyone in this infrastructure gold rush is Nvidia; there are also many small key players. Today, we will delve into Astera Labs, a company whose chips are quietly used in over 80% of AI servers.

Astera Labs is a pure data center connectivity company, primarily targeting three types of customers: hyperscale enterprises, AI accelerator vendors, and system OEMs. Astera Lab's product portfolio currently consists of three series: Aries Retimers, Taurus Active Electrical Cable (AEC) paddle board modules, and Leo CXL memory controllers.

Looking back historically, connectivity is a fiercely competitive and highly profitable part of the data center market. Despite multiple competitions in the switching and DSP fields, Broadcom and Marvell have been able to dominate with over 80% revenue share and over 65% gross margin.

In the tech industry, the first-mover advantage is not crucial; what matters is the technology. We will discuss the key competitors in all major markets where Astera Labs operates, including Marvell Technologies, Broadcom, Montage Technology, Parade Technologies, Rambus, Microchip, XConn, and Credo. Astera Labs may fade away gradually, or if they maintain a high share of the retimer market and expand into AEC and various CXL products, they could become the next connectivity superhero.

How Astera Labs Solves Connectivity Issues

Astera Labs was founded in a garage in 2017, with a typical Silicon Valley style. Co-founders Jitendra Mohan, Sanjay Gajendra, and Casey Morrison previously worked in Texas Instruments' high-speed interface business unit. They saw that as computational demands grow exponentially, and heterogeneous computing needs driven by AI workloads and hyperscale cloud computing increase, the world's connectivity bottlenecks are becoming more severe.

Astera Labs is dedicated to eliminating bottlenecks, wherever they occur in the system The following figure shows the 3 main issues that Astera Labs aims to address.

The company's initial focus was on PCIe and related protocols such as CXL. The PCIe 4.0 specification was released in 2017, formally defining the terms "redriver" and "retimer" for the first time. A redriver is essentially an analog signal amplifier device used to counteract frequency-dependent attenuation caused by the PCB.

In simple terms, it can enhance signals, much like a "loudspeaker." The main drawback of redrivers is that they also amplify noise in the signal path. This works well for PCIe Gen 1 to Gen 3, but poses challenges starting from Gen 4, with the faster data rates of Gen 5 exacerbating the situation. The figure below shows the per-inch loss for different PCIe generations and PCB materials.

To compensate for signal loss, the preferred approach is to use higher-quality PCB materials, but this comes at a high cost. For example, the cost of the PCB material "Megtron 6" is approximately seven times that of the most popular and cost-effective PCB material, "FR4."

It is important to note that the PCIe specification has precise insertion loss budgets; in the case of PCIe 5.0, the collision-to-collision noise at 32 GT/s is 36 dB, with a bit error rate of less than 10^-12.

Astera Labs is dedicated to addressing the connectivity challenges of PCIe 4 and 5 (specifications released in 2019). They have established a company around solving these signal integrity challenges and designing solutions based on retimers. A retimer is a mixed-signal digital/analog device with protocol-aware capabilities that can fully recover data, extract embedded clocks, and retransmit clean data with a fresh copy of the signal.

In essence, it is not a "loudspeaker" like a redriver, but a high-quality microphone + dedicated audio device that feeds the corrected signal from speaker to speaker. The retimer is a small chip that performs PCIe SerDes functions as well as monitoring signal integrity and collecting data. The figure below shows a typical architecture.

The retimer can divide the signal into two channels, significantly reducing channel loss. The figure below shows how these chips are integrated into the PCB. This also indicates that low-loss PCBs, or even ultra-low-loss PCBs, may not be sufficient to achieve the desired channel loss.

Astera Labs was the first to introduce the Aries intelligent retimer for PCIe 4.0 and PCIe 5.0 to the market, winning its first design victory in 2019. Mass production began in 2020 using TSMC technology, and the company generated $34.8 million in revenue in 2021. They have a group of excellent investors, such as Fidelity, Atreides Management, Intel Capital, and Sutter Hill Ventures. Their last round of financing before this IPO was conducted after rejecting Marvell's acquisition offer.

Astera unveiled its vision of providing a global connectivity platform and launched two additional product lines: CXL memory controllers and intelligent cable modules. The figure below illustrates Astera Lab's vision.

At the beginning of 2023, they took a wrong turn, with soft and declining performance in the first and second quarters, impacted by inventory adjustments affecting the general data center and network markets, while the cloud crisis of the largest hyperscale customers drove this market. But this is not the end of the story, with explosive growth in the third quarter of 2023 and the fourth quarter of 2024. So, what happened there? Is this situation sustainable?

To answer this question, let's delve deeper into the Aries product line and its key applications.

Aries Retimers for AI and Cloud Applications

In short, the answer is yes: as the demand for AI accelerators continues to grow, the PCIe retimer market will also grow. In fact, each accelerator card contains an internal retimer. Other retimers can be found in server head nodes, as shown in the figure below. The main customers here are AI accelerator suppliers and server ODMs.

The reason why re-timers are so popular in accelerated computing systems is signal reflection. In addition to distance, this is the second major reason for signal loss in PCB routing or cables. In short, GPU systems are very dense: the diagram above shows how a backplane (such as Nvidia HGX) contains 8 GPUs. Such density brings signal challenges and requires PCIe re-timers. AI servers can include re-timers on accelerator boards and connected server head nodes. The exact number of units per GPU depends on various factors such as PCB and design layout, and we will share our estimates with subscribers in a later report. Different hyperscale designs contain different numbers of re-timers.

Astera Labs' first major customer is actually Amazon, providing "typical" (non-AI) cloud workloads. In some cases, Aries re-timers can help cloud service providers achieve lower TCO than high data rate alternative solutions. The image below shows the location of re-timers in IT equipment.

Another driver for the upcoming Aries is CXL, a protocol built on top of PCIe. The adoption of CXL in memory pools will lead to an increasing demand for CXL switches, which will require re-timers