News: Taiwan Semiconductor is expected to launch 2nm process MPW services in September, attracting downstream enterprises to seize the opportunity and layout in advance
Taiwan Semiconductor is expected to launch the first round of 2nm process MPW services in September, attracting downstream design companies to participate in the layout. MPW can integrate chip designs from multiple customers onto the same test wafer, reducing costs and speeding up verification. The production cost of 2nm wafers is expected to be between $24,000 and $25,000, putting pressure on small and medium-sized design companies. This service can significantly reduce prototype design costs and verify circuit functionality and process compatibility. IC design companies are calling on Taiwan Semiconductor to help customers adapt to new technologies
On August 29th, IT Home reported that Taiwan's Commercial Times stated that Taiwan Semiconductor is set to launch its MPW service every six months starting in September, with this round of MPW service expected to offer a 2nm option for the first time, attracting downstream design companies to take the lead in layout.
MPW, short for Multi-Project Wafer, gathers chip design samples from multiple customers onto the same test wafer for production, which can share wafer costs and quickly complete chip trial production and verification. Taiwan Semiconductor refers to MPW as the CyberShuttle wafer sharing service.
According to Taiwanese media reports, the price per wafer for Taiwan Semiconductor's 3nm process has reached about $20,000 (approximately RMB 143,000 at the current exchange rate). In the future, the price per wafer for 2nm is expected to reach $24,000 to $25,000 (approximately RMB 171,000 to 178,000), posing a heavy burden for small and medium-sized design companies without fabs.
Taiwan Semiconductor mentioned on its official website that using the CyberShuttle service can reduce prototype design costs by up to 90%; furthermore, this service can also verify the sub-circuit functions and process compatibility of IP, standard cell libraries, and I/O systems.
N2 is Taiwan Semiconductor's first GAA transistor node, which has significant differences in structure compared to FinFET. IC design companies believe that it is necessary for Taiwan Semiconductor to familiarize customers with the changes brought by GAA as soon as possible, as 2nm chips and 3D packaging test chips will be mass-produced in 2025
