Taiwan Semiconductor's 2nm production capacity is in crisis: Apple secures the first batch, AMD and Google are in line, and NVIDIA has already set its sights on 1.6nm

The competition for TSMC's most advanced process capacity has officially begun. Global tech giants are accelerating their entry into the 2nm process node, which has been fully booked, while advanced packaging supply is tightening simultaneously, highlighting the ongoing pressure on the semiconductor supply chain from the combined demand for AI and mobile chips.

NVIDIA CEO Jensen Huang stated during a dinner with core supply chain executives on January 31 that TSMC must operate at full capacity this year, directly pointing out the tight situation regarding advanced process capacity. This statement confirms the industry's judgment that TSMC's 2nm capacity is in urgent demand.

According to reports citing industry insiders, Apple has secured more than half of the first batch of 2nm capacity, with Qualcomm also being a major customer for 2026. AMD plans to start production of 2nm-based CPUs in 2026, while Google and AWS are targeting the introduction of this process in the third and fourth quarters of 2027, respectively. NVIDIA is looking ahead to 2028, with its Feynman AI GPU expected to use TSMC's A16 process, which integrates back power delivery technology.

The tight capacity situation is expected to continue until 2027. AI accelerators and mobile processors are competing for limited capacity, while challenges in advanced packaging yield further exacerbate the supply-demand imbalance. Institutional investors expect TSMC's CoWoS monthly capacity to grow by over 70% year-on-year in 2026, but it will still be difficult to meet market demand.

Mobile chips occupy initial capacity, AI customers to ramp up significantly in 2027

According to reports, both TSMC's 2nm and 3nm process nodes are facing capacity constraints, with high-performance computing and mobile chips competing for limited supply. The main customers for 2nm in 2026 are Apple and Qualcomm. According to sources cited by Wccftech, Apple has secured more than half of the first batch of 2nm capacity.

Starting in 2027, general-purpose GPUs and custom ASICs will ramp up more widely. Analysts point out that this includes AMD's MI series GPUs, Google's eighth-generation TPU, and AWS's Trainium 4. Industry insiders expect TSMC's 2nm family to become a long-lifecycle node, with initial capacity ramp-up potentially exceeding that of the 3nm generation.

The N2 process is set to enter mass production in 2026, with N2P and A16 processes following in the second half of the year. The A16 process is aimed at specific high-performance computing products that require complex wiring and high-density power delivery.

NVIDIA skips 2nm and heads straight to 1.6nm, betting on back power delivery technology

NVIDIA's process roadmap shows a different strategy. According to reports, the company plans to launch the Feynman AI GPU in 2028, which is expected to use TSMC's A16 process, characterized by back power delivery technology.

The A16 process represents TSMC's 1.6nm node, designed specifically for high-performance computing products. Back power delivery technology moves the power transmission network to the back of the chip, improving signal integrity and enhancing power transmission efficiency, which is particularly critical for large AI accelerators.

This timeline suggests that NVIDIA may skip or only adopt the 2nm process on a small scale, directly transitioning to more advanced nodes, reflecting the aggressive pursuit of process technology by AI chip manufacturers

Advanced packaging becomes a new bottleneck, CoWoS capacity growth still lags behind demand

Capacity tightness is not limited to the wafer foundry segment. Reports indicate that TSMC is upgrading its advanced packaging ecosystem. As AI chips fully enter the era of chiplet architecture and ultra-large packaging sizes, single-chip designs can no longer meet computing power demands, and CoWoS-L, SoIC, and hybrid bonding technologies have effectively become standard.

According to reports citing institutional investors, TSMC aims for a more than 70% year-on-year increase in CoWoS monthly capacity by 2026, while gradually validating next-generation technologies such as CoWoP (Chip-on-Wafer-on-PCB) and CPO (Co-Packaged Optics).

However, the supply-demand imbalance remains a key bottleneck. In addition to the tight capacity for 2nm foundry services, improving the yield of large-scale system-level packaging is another significant challenge. As the packaging size of AI chips continues to expand, maintaining high yields becomes significantly more difficult, which may further constrain the supply capability of advanced chips