AI Computing Bottleneck Easing? Report: Taiwan Semiconductor CoWoS Gap to Drop from 20% to 10%

Taiwan Semiconductor continues to expand its advanced packaging capacity, offering hope that bottlenecks in the AI chip supply chain will gradually ease.

Citing views from institutional investors, media reports indicate that as Taiwan Semiconductor and its partners actively expand advanced packaging capacity, the CoWoS supply-demand gap is expected to narrow significantly from the current approximately 20% to around 10% by the end of 2026, with further improvements likely in 2027. This progress has a direct impact on the supply chain for AI accelerators that rely on CoWoS packaging technology.

At the same time, Taiwan Semiconductor is advancing the R&D layout for its next-generation packaging platform, CoPoS (Chip-on-Panel-on-Substrate). It is reported that NVIDIA's Feynman platform is expected to be among the first customers to adopt this technology, with a mass production window pointing to 2028–2029.

Capacity Expansion Accelerates, Supply-Demand Gap Narrows Rapidly

According to TrendForce, Taiwan Semiconductor's average monthly CoWoS capacity is expected to reach 120,000 to 140,000 wafers in 2026, setting a new historical high. If the additional monthly capacity of 50,000 to 60,000 wafers from outsourced semiconductor assembly and test (OSAT) partners is included, the total industry monthly capacity could approach 200,000 wafers.

TrendForce predicts that the severe shortage of global 2.5D packaging capacity will begin to ease in 2027, supported by factors such as the spillover effect of orders and Taiwan Semiconductor's plan to expand CoWoS capacity by more than 60% in 2027.

According to Reuters, Taiwan Semiconductor predicted at a technical seminar held in May this year that CoWoS advanced packaging capacity would achieve a compound annual growth rate of over 80% between 2022 and 2027, further confirming the scale and intensity of this round of expansion.

Next-Generation Platform CoPoS Accelerates Deployment, NVIDIA Expected to Be Early Adopter

While continuing to expand existing CoWoS capacity, Taiwan Semiconductor is also paving the way for its next-generation advanced packaging platform, CoPoS. As wafer sizes continue to increase, CoPoS is seen as a key path to breaking through the ceiling of existing technology.

Taiwan Semiconductor established a CoPoS R&D production line at its subsidiary VisEra in 2025. Material and equipment certification work is expected to be completed as early as June 2026, with pilot mass production targeted for mid-2027.

According to TrendForce, NVIDIA's Feynman platform is expected to become the first commercial customer for CoPoS technology. The platform is projected to enter full-scale mass production between 2028 and 2029, with main deployment sites including Taiwan Semiconductor's Chiayi facility and its wafer fab in Arizona, USA.

Market Significance: Key Bottleneck in AI Supply Chain Expected to Ease

CoWoS packaging technology is a core process in the production of current high-end AI accelerators. The tightness of its capacity directly affects the shipment pace and delivery cycles of downstream AI chips. The narrowing of the supply-demand gap from 20% to 10% means that the key link previously constraining the expansion of AI computing hardware is loosening, helping to alleviate market concerns about the supply of AI infrastructure.

From a longer-term perspective, the advancement of the CoPoS platform supports Taiwan Semiconductor in building a deeper technological moat in the field of advanced packaging, further consolidating its core position in the AI chip supply chain.