TSMC to Expand PIC Capacity 30-Fold in Three Years, CPO Supply Chain Enters Window of Opportunity for Volume Ramp-Up

The leapfrog expansion of Taiwan Semiconductor's photonic integrated circuit (PIC) capacity is pushing co-packaged optics (CPO) from the laboratory into the stage of scaled mass production, opening a new growth window for the entire AI optical communication supply chain.

According to a report by the Commercial Times of Taiwan on Wednesday, brokerage firms estimate that TSMC's PIC (photonic integrated circuit) monthly capacity will rapidly increase from the current approximately 500 wafers to 10,000 wafers in the second quarter of 2026, 15,000 wafers in the fourth quarter, and further rise to at least 25,000 wafers by 2028, expanding more than 30-fold within three years.

Calculated at 648 dies per wafer, annual PIC output will jump from about 4 million units to a peak of nearly 194 million units, with estimated actual optical engine shipments reaching 48.6 million units.

The direct beneficiaries of this capacity expansion are initially concentrated among top-tier customers. Brokerages predict that from 2026 to 2027, the main mass-production customers for TSMC's COUPE platform will be NVIDIA, Broadcom, and AMD. As capacity further ramps up in 2028, CPO projects from customers such as MediaTek, Marvell, and Ayar Labs are also expected to be included in the mass-production platform. Meanwhile, demand in downstream segments such as FAU, lasers, optical testing, probe cards, test sockets, and automation equipment will heat up in tandem with the volume ramp-up of PICs.

Behind the Three-Stage Capacity Leap: AI Computing Power Drives Surge in Optical Engine Demand

PIC is the core component of CPO optical engines, responsible for the conversion, guidance, and coupling of electrical and optical signals. As the scale of AI server clusters continues to expand, switch bandwidth is evolving from 25T and 50T to 100T and 200T, driving a simultaneous rise in demand for optical engines. Consequently, progress on TSMC's COUPE platform has become a key focus for market tracking.

Brokerages point out that this round of PIC capacity expansion by TSMC holds triple strategic significance:

First, it marks the formal transition of CPO from the experimental and small-batch validation stages into the preparation phase for mass production;

Second, the deep integration of silicon photonics with advanced packaging will enable COUPE, SoIC, and CoWoS to jointly constitute a more complete AI optoelectronic integration platform;

Third, the volume ramp-up of PICs will drive increased demand across the entire supporting supply chain, covering multiple segments including FAU coupling, lasers, optical testing, and automation equipment.

Multiple Processes to Navigate, Variability Remains in Ramp-Up Pace

Although the path for capacity expansion is clear, brokerages also caution that an increase in PIC capacity does not equate to an immediate full-scale volume ramp-up of CPO. After PIC wafers are completed, subsequent stages must sequentially pass through SoIC integration, optoelectronic testing, optical engine packaging, FAU coupling, and system-level verification. Each step constitutes a potential variable affecting yield and schedule.

Taking brokerage estimates as an example, under a scenario assuming a 50% SoIC yield, a monthly capacity of 10,000 wafers would correspond to an optical engine output of approximately 2 million units. If further losses from downstream assembly yields are factored in, actual shipments would narrow further to about 390,000 units.

This implies significant yield loss between wafer capacity and final shipments. The ability of various supply chain segments to ramp up yields will largely determine the actual pace and magnitude of the CPO volume ramp-up.