"Disrupting" HBM? Intel XBM Patent Revealed: Focusing on Low Packaging Costs
Intel has disclosed a patent for its XBM memory, which replaces the HBM silicon interposer with UCIe serial interconnects and back-end DRAM architecture, aiming to reduce packaging costs while increasing bandwidth and density. However, commercialization is not expected until after 2030, making it unlikely to shake the HBM ecosystem dominated by SK Hynix and Samsung in the short term
Intel is seeking to challenge the dominance of High Bandwidth Memory (HBM) with a new memory architecture, but its commercial prospects remain distant.
A patent application published by Intel last week revealed its "Cross-Batch Memory" (XBM) architecture. The design aims to bypass the reliance of existing HBM on silicon interposers by replacing traditional DRAM and its ultra-wide interfaces with back-end process transistors and serial UCIe interconnects, thereby significantly reducing packaging costs.
According to Wccftech, the target timeline for the commercialization of XBM is set for after 2030, aligning with the schedule for the ZAM memory architecture jointly developed by Intel and SAIMEMORY, a subsidiary of SoftBank.
The HBM market is currently dominated by South Korean manufacturers. The dual pressures of tight supply and high costs are driving the industry to seek alternatives. Intel's patent disclosure adds a new variable to this competitive landscape, but analysts point out that ecosystem barriers and platform compatibility issues will be the main obstacles for XBM's market entry.
XBM Architecture: Replacing Wide Parallel Interfaces with UCIe Serial Interconnects
According to the patent, the core of the XBM architecture lies in connecting DRAM modules to UCIe I/O modules operating at a rate of 32 GT/s, with I/O signals routed through a base die.
The single-die capacity of each XBM stack ranges from 0.5GB to 5GB; each sub-channel consists of 12 data modules. An 8-layer XBM stack can accommodate up to 96 data modules, while a 16-layer stack can reach 192, with channel operating frequencies of 2GHz.
In terms of packaging, XBM supports various configurations, including Memory-on-Package (MoP), which enables higher bandwidth and capacity within a smaller form factor. This flexibility is seen as one of the potential advantages of XBM over existing HBM solutions.
Back-End DRAM Process: Improving Area Efficiency and TSV Density
A key innovation of XBM at the process level is the adoption of a 1T1C (one transistor, one capacitor) back-end DRAM structure.
According to Wccftech, this approach manufactures transistors in the Back-End-of-Line (BEOL) metal layers rather than on the front-end silicon substrate, significantly improving area efficiency. This frees up more space for Through-Silicon Vias (TSVs), thereby achieving higher memory density and bandwidth.
This design directly addresses the core pain points of existing HBM. According to an analysis by Global Economic News cited by TrendForce, traditional HBM requires micro-bump processes when vertically stacking DRAM chips, resulting in high manufacturing costs; silicon interposers further increase wiring complexity and overall costs. The XBM architecture is proposed specifically to resolve these limitations.
SK Hynix and Samsung's First-Mover Advantage Is Hard to Shake
Although XBM possesses certain technical attractions, its impact on the existing competitive landscape remains questionable.
As pointed out by Global Economic News, SK Hynix and Samsung Electronics have been deeply engaged for several years in cost-reduction technologies such as standard chiplets, UCIe, and fan-out packaging, accumulating considerable first-mover advantages in cost optimization.
A more critical obstacle lies at the ecosystem level. The global AI accelerator ecosystem, centered around Nvidia, is already highly adapted to the existing HBM architecture and its wide parallel interfaces. Migrating to an alternative memory architecture faces high platform compatibility and software adaptation costs. This means that even if XBM is competitive in technical specifications, its large-scale commercial deployment must still overcome significant industry inertia.
The commercialization window for XBM is expected to open after 2030. This implies that in the foreseeable future, HBM will remain the mainstream solution for the high-bandwidth memory needs of AI chips. Intel's patent represents more of an exploration of a technological direction rather than an immediate shock to the existing market landscape.
