The "Three Arrows" of Domestic Computing Power: Chips, FABs, and Super Nodes

The main theme of domestic computing power is no longer just a single-point issue of "how much performance a certain chip has caught up with." More critical are three things: whether domestic AI chips can be delivered at scale, whether advanced manufacturing can handle the surge in demand, and whether, when single-card performance is limited, super nodes can convert multi-card computing power into truly usable system computing power.

Xue Hongwei, an electronics industry analyst at Guolian Minsheng Securities, wrote in an industry research report on July 21: "Currently, the domestic computing power industry is seeing significant improvements on both the supply and demand sides, and the rise of domestic computing power has become one of the important trends in industrial development. We recommend focusing on the 'Three Arrows': Chips, FABs, and Super Nodes." This framework breaks down the core contradictions of domestic computing power: demand is rising, supply needs to be supplemented, and system architecture must also be upgraded.

Changes on the demand side are direct. Domestic large models continue to iterate, Token call volumes are growing rapidly, and leading cloud vendors' capital expenditures are continuing to tilt towards AI; on the supply side, overseas high-end AI chips and advanced manufacturing paths remain restricted, further increasing the pressure for domestic substitution. In 2025, China's total shipments of AI accelerator cards will be approximately 4 million units, of which domestic AI chips will account for about 1.65 million units, with their share exceeding 40% for the first time.

Under this framework, chips represent the front-end elasticity of volume expansion, foundries serve as the foundation for capacity and process technology, and super nodes address the issue of "how to strengthen the system when a single card is not powerful enough." Investment clues are thus expanding from AI chip manufacturers to wafer foundries, PCIe Switches, Ethernet switching chips, high-speed SerDes, optical communications, and complete machine systems.

Domestic AI Chips: Moving from Product Verification to Scale Delivery

The adaptation between domestic large models and domestic chips is accelerating. In April 2026, DeepSeek V4 was released and open-sourced, having completed adaptation for domestic chips such as Hygon, Huawei Ascend, Kunlunxin, and Moore Threads. In July, Meituan open-sourced LongCat-2.0—a trillion-parameter model trained end-to-end on a cluster of 50,000 domestic computing cards, with 1.6T total parameters and an average activation of about 48B, proving that the collaborative training of domestic large models and domestic computing power is viable.

Token call volume is the hardest indicator on the demand side. OpenRouter data shows that from March 16 to 22, 2026, the platform's weekly Token call volume reached 20.4 trillion, a month-on-month increase of 20.7%; the average weekly usage in February 2026 had already exceeded twice that of the fourth quarter of 2025. Agent scenarios will further amplify computing power consumption: the Token consumption for a single Agent to complete a typical task is about 4 times that of ordinary conversation, while multi-Agent collaboration systems can reach 15 times.

Cloud vendors' capital expenditures are also following this curve. In the first quarter of 2026, the combined capital expenditures of BAT (Baidu, Alibaba, Tencent) increased by 17.7% year-on-year to RMB 64.746 billion, a 28.03% increase compared to the fourth quarter of 2025. ByteDance raised its 2026 capital expenditure plan to RMB 160 billion, with about RMB 85 billion directly invested in AI chip procurement; Alibaba proposed investing RMB 380 billion over the next three years to build cloud and AI infrastructure; Tencent's operating capital expenditure in the first quarter of 2026 was RMB 31.2 billion, a year-on-year increase of 18% and a month-on-month increase of 84%.

On the supply side, domestic AI chip manufacturers are completing their product matrices. Huawei Ascend shipped about 812,000 units in 2025, accounting for nearly 50% of domestic AI chip shipments, with subsequent roadmaps planned up to Ascend 910C, 950PR, 950DT, 960, and 970. Cambricon covers cloud training, cloud inference, and edge scenarios, with its Siyuan 590 using a 7nm process and INT8 computing power reaching 512 TOPS; Hygon focuses on "general-purpose computing + AI integration," with its DeepCalc DCU compatible with CUDA-like environments; MetaX's MXC600 focuses on integrated training and inference, adopting a fully domestic supply chain; and Iluvatar CoreX covers three series: training, inference, and edge.

ASIC is also a line worth looking at separately. Cloud-side computing power demand no longer relies solely on general-purpose GPUs; chips customized for specific models, algorithms, and application scenarios offer better energy efficiency and cost control space in inference and data center high-performance computing scenarios. VeriSilicon, relying on its platform capabilities of "IP licensing + chip customization services + chip mass production services," has seen clear reflection on the order side: From January to April 20, 2026, orders on hand reached RMB 5.133 billion, continuing the trend of consecutive historical highs from the second to the fourth quarters of 2025, with the majority coming from one-stop chip customization business, mainly from cloud-side AI ASICs and IP.

Foundries: The More Restricted Advanced Manufacturing Is, The More Important the Local Foundation Becomes

For domestic AI chips to move from verification to delivery, wafer manufacturing is unavoidable. In recent years, the United States has continuously strengthened export controls around advanced computing chips and semiconductor manufacturing capabilities, including logic chips of 16/14nm and below in the advanced node-related control framework, and restricting the export of advanced semiconductor manufacturing equipment.

The space on the demand side is equally clear. According to statistics from the China Academy of Information and Communications Technology and Frost & Sullivan, the market size of China's intelligent computing chips is expected to grow from USD 30.1 billion in 2024 to USD 201.2 billion in 2029, with a CAGR of 46.3% from 2024 to 2029; among them, the GPGPU market will have a CAGR of 49.0% during the same period. Beyond AI chips, Huawei proposed the Taolaw, expecting that by 2031, the transistor density of high-end chips based on this path is expected to reach the equivalent level of 1.4nm process technology.

SMIC is the core object of observation in this link. In the first quarter of 2026, the company's revenue was RMB 17.62 billion, a year-on-year increase of 8.1%; net profit attributable to shareholders was RMB 1.36 billion, a year-on-year increase of 0.4%. The proportion of 12-inch wafer revenue reached 76.4%, and the proportion of revenue from China reached 88.9%; monthly capacity reached 1.078 million 8-inch equivalent wafers, a year-on-year increase of about 10.8%, with a capacity utilization rate of 93.1%, still at a high level.

Hua Hong Semiconductor's data reflects the resilience of its specialty process platform. In the first quarter of 2026, the company's sales revenue was USD 660 million, a year-on-year increase of 22.2%; gross margin was 13.0%, a year-on-year increase of 3.8 percentage points; net profit attributable to shareholders was USD 20.9 million, a year-on-year increase of 458.1%. The proportion of 12-inch revenue increased to 62.7%, with an 8-inch equivalent monthly capacity of 489,000 wafers and a capacity utilization rate of 99.7%.

Nexchip continues to expand its 12-inch specialty process platform. In the first quarter of 2026, the company's revenue was RMB 2.91 billion, a year-on-year increase of 13.4%; net profit attributable to shareholders was RMB 50.659 million, a year-on-year decrease of 62.6%, with profits affected by declining product prices and increased depreciation of fixed assets. DDIC remains the core business, while CIS, PMIC, and Logic are gradually broadening, 28nm OLED products are undergoing continuous verification, and the 28nm logic process platform has completed development and entered the customer tape-out stage.

Super Nodes: Not Simply Stacking Cards, But Turning Multi-Cards into System Computing Power

Single-card performance is no longer sufficient to determine the actual performance of AI clusters. As large model parameter scales expand and architectures evolve with MoE and long context, cluster requirements for memory bandwidth, inter-chip communication, and interconnection latency have significantly increased. The importance of Scale-up has therefore risen: connecting more AI processors, CPUs, memory, and storage resources into a unified computing resource through high-speed interconnects to improve multi-card collaboration efficiency.

Super nodes are a further evolution based on Scale-up. They use high-speed interconnects to compose multiple server nodes into a unified computing domain, allowing AI processors distributed across different servers to collaborate computationally like a single entity. Compared to traditional server clusters that manage resources on a per-machine basis, super nodes can break through the limit on the number of AI processors deployable in a single server, reduce cross-node communication overhead, and improve resource scheduling efficiency.

Huawei's CloudMatrix384 is one representative solution. This architecture is based on 384 Ascend NPUs and 192 Kunpeng CPUs, shifting from server-level resource supply to matrix-level resource supply. Multiple computing nodes no longer provide computing power individually but form a unified resource pool, allowing computing, memory, and network resources to be dynamically combined according to task requirements. Its Unified Bus supports communication-intensive tasks such as expert parallelism and distributed KV Cache access.

Domestic super nodes have moved from R&D verification to mass production ramp-up. Currently, domestic CSP super nodes are entering the mass production ramp-up phase, and leading manufacturers are gradually initiating subsequent super node tenders. With the iteration of in-house chips by major companies, the increase in capacity of third-party domestic chips, and the growth in Agent inference demand, super nodes are expected to become the main deployment form of next-generation AI infrastructure.

The role of complete machine manufacturers is also changing. Super node cabinets supporting Ascend 950 and self-developed chips by internet giants are expected to gradually enter the stage of scale delivery. Super nodes raise the barriers for supply chain management, system design, integration verification, and delivery, meaning complete machine manufacturers are no longer just assembly and delivery roles.

High-Speed Interconnects Become a New Bottleneck, Pushing Switching Chips to the Forefront

The core of super nodes is not "more cards," but "more efficient interconnects." As GPU cluster scales continue to expand from GB300 NVL72 to Rubin Ultra NVL576, AI infrastructure is beginning to shift from being driven by traditional Scale-out to a collaboration between Scale-up and Scale-out. Scale-up is responsible for high-bandwidth, low-latency interconnects between GPUs within a super node; Scale-out is responsible for interconnects between super nodes and at the data center level.

LightCounting data shows that the global market size for Scale-up switching chips is expected to approach USD 18 billion by 2030, with a compound annual growth rate of 28% from 2022 to 2030. Domestic AI servers are also driving demand for PCIe switching chips; according to calculations based on information from Wontop Development's announcement, the market size for PCIe switching chips in China's AI server sector was about RMB 3.8 billion in 2024 and is expected to grow to RMB 17 billion by 2029.

PCIe Switch is an important chip for high-speed interconnects within servers, responsible for high-bandwidth, low-latency data exchange between CPUs, GPUs, storage, and other devices. Montage Technology has launched PCIe 6.x/CXL 3.x AEC solutions and is developing next-generation products such as PCIe 7.0 Retimers and high-speed Ethernet PHY Retimers; Shudu Technology's self-developed PCIe 5.0 104-lane high-speed switching chip has achieved mass production; VeriSilicon is also accelerating its layout of interface IP, with its high-speed SerDes interface IP having achieved tape-out.

Ethernet switching chips are responsible for high-speed packet switching and forwarding over a larger scope. Centec Communications' 12.8Tbps and 25.6Tbps high-end flagship chips have entered the market promotion and application phase, supporting port speeds of up to 800G. ZTE Microelectronics released its self-developed AI switching chip "Lingyun" in 2025, capable of supporting smart computing clusters of ten thousand or even one hundred thousand cards, while also exhibiting the Tianyi series of Ethernet switching chips with a maximum switching capacity of 12.8Tbps.